Computer display systems, especially those with bit-mapped graphic capabilities, have gained widespread popularity in recent years due to the proliferation of personal computers, high levels of functional integration in graphic display systems, and increasing capability and decreasing cost of computer graphics interfaces and color video monitors.
Bit-mapped computer graphics display systems are characterized by a video frame buffer memory which contains a digital representation of an image to be displayed. The memory is organized such that each group of "n" bits represents a single dot or "pixel" on a display screen. The "n" bits associated with each pixel determine its intensity, color, or other attribute. This direct mapping of bits to individual display pixels is the source of the name "bit-mapped". In normal operation, an image stored in a video frame buffer memory is displayed by rapidly accessing the pixel data in the memory in a raster-scan (e.g., left-to-right, top-to-bottom) order, and presenting this data to a video monitor repeatedly in a serial video stream. While some monitors accept a multi-bit digital video stream, others require that the digital data be converted to an analog form for display. This is usually accomplished in a DAC (Digital to Analog Converter) whereby multi-bit digital pixel data is converted to one or more analog intensity (brightness) signals. For color displays, three analog intensity signals are typically used, one for each of the three primary colors of light: red, blue and green. One or more synchronizing signals are used to synchronize the video monitor to the start of the memory access cycle so that each pixel is displayed in a fixed or pre-determined position on the monitor screen.
Exemplary of bit-mapped graphics systems currently in use are "VGA" controllers, widely used in personal computer graphics applications. A typical modern VGA (Video Graphics Array) color graphics system for an ISA personal computer (Industry Standard Architecture, sometimes referred to as "IBM compatible") has up to 1 Mbyte (1,048,576 bytes) of video frame buffer memory and is capable of displaying up to 256-color graphics images at a displayed resolution of up to 1024.times.768 pixels (picture elements or dots).
FIG. 1 is a block diagram of a typical VGA interface 100 (a bit-mapped graphics display controller) for a personal computer. An integrated video controller 105 interfaces between a host computer (not shown) via address lines 120, data lines 125, and control lines 115. These address, data, and control lines, 120, 125, and 115, respectively, permit the host computer to read and write registers located within the video controller 105. The data bus (i.e, the collection of data lines) is shown as 16 bits wide, indicating a connection to a host computer with a bus width of at least 16 bits (typical of ISA computers). A clock synthesizer 110, provides master timing for the video controller 105. The integrated video controller 105 is implemented as a single chip.
A notational convention for indicating bus width (the number of signals carried between two functional blocks in a block diagram) is used herein whereby a number immediately to the left of a diagonal slash "/" through a line indicates the number of signals or wires (bus width) associated with the line. This convention is reflected in the Figures.
The video controller 105 generates video timing signals and provides access to an external (to the video controller) video frame buffer memory 130. In FIG. 1, the video frame buffer memory 130 comprises eight 256K.times.4 (262,144.times.4) dynamic RAM (DRAM) memory chips 130a-130h, providing a total of 1 Mbyte (1,048,576.times.8) of total available video frame buffer memory, organized as a 256K.times.32 bit memory. Each DRAM chip 130a-130h has a corresponding set of four data I/O lines 132a-132h connected to the video controller 105, for a total video bus width (width of the video frame buffer memory unit of exchange with the video controller 105) of 32 bits. The video controller 105 governs all access to the video frame buffer memory 130, and generates an 18 bit address on lines 134, provided in common to all of the video memory chips 130a-130h.
The integrated video controller 105 accesses the video frame buffer memory 130 for two purposes: 1) to store and/or retrieve pixel data to/from the video frame buffer memory 130 as commanded by the host computer; and 2) to display the pixel data stored in the memory on a video monitor. Video monitors require that the displayed image be periodically refreshed, so the video controller 105 must repeatedly scan through the pixel data in the video frame buffer memory 130. Computer access to the frame buffer memory 130 must be interleaved between the display refresh accesses, thus limiting the amount of time the frame buffer memory is available to the computer.
The integrated video controller 105 itself contains three functional blocks: a video controller core 106, a FIFO 107a, a memory access control functional block 107b, and a video shift register 108. The video controller core 106 contains registers and logic which implement the basic video timing and interface to the host processor. The FIFO (First-In, First-Out buffer) and memory access control functional block manages all accesses to the video frame buffer memory, and performs the memory accesses required for display refresh, interleaving host computer pixel data, buffered in the FIFO, with the display refresh accesses. The memory access controller permits programmed (host computer) access to the video frame buffer memory in between display refresh accesses (if any such access time is available) and during vertical and horizontal retrace intervals (the time periods when the display "beam" is resetting itself to scan another row of pixels or between images).
For display refresh, the video frame buffer memory 130 is accessed 32 bits at a time. The 32 bits of video data is then placed in a video shift register 108 internal to the video controller 105 and shifted out in a serial video stream on lines 142. The serial video stream (i.e., 142) as shown is 8 bits wide, indicating a capability of displaying up to 256 colors or intensity values for each pixel. A RAM-DAC 140 (Random Access Memory-Digital to Analog Converter) converts the digital pixel data on lines 142 to one or more analog video signals 144 for a video monitor (not shown). A synchronizing signal 146 (Sync) is generated by the video controller 105 to synchronize the video monitor to the video frame buffer access cycle.
While the discussion hereinabove with respect to FIG. 1 makes reference to a VGA-type bit-mapped graphics controller (video controller), the discussion applies to bit-mapped graphics controllers in general, and is not intended to limit the field of this specification to VGA-type controllers or to ISA-type computers. The discussion hereinafter is of a more general nature.
On early video systems, the computer could only gain access to the video frame buffer memory during brief periods of time, because the video refresh access dominated access to the video frame buffer memory. This led to very slow screen update speeds. In response to this, some early systems provided rapid access to the video frame buffer memory by shutting down the video display while an image was being refreshed, causing "video flicker" while new pixel data was being written to or read from the video frame buffer memory. Other early systems would simply over-ride the video refresh access while the frame buffer memory was being read or written by the host computer, causing erratic display dots or "video snow" to appear on the video monitor during computer access to the frame buffer memory.
While this did improve display speed, the resulting erratic displays were considered annoying at best, and unacceptable at worst. It is a requirement of virtually all modern video display systems that "transparent" access (access without disruption of display refresh operations) be provided to the video frame buffer memory. This, of course, requires a faster effective video frame buffer access time, implying faster memories or faster memory access techniques.
A significant factor in the cost of memory chips used in video display subsystems is access time. In general, the faster the memory, the higher the chip cost. DRAMs (Dynamic Random Access Memories) are usually the least expensive type of memory available for such applications. While DRAMs require periodic "refreshing" of memory locations, the repeated serial-access nature of the video refresh memory access provides a natural mechanism for refreshing DRAMs transparently.
One technique which is used to provide faster "apparent" video memory speed is to provide a very wide video memory bus. In the video system of FIG. 1, the video memory bus width (132a-h) is 32 bits. This means that 32 bits of pixel data are accessed at once. If there are 8 bits of pixel data per pixel, this means that video memory need be accessed only once every four pixels. However, at extremely high non-interlaced display resolutions (e.g. 1024.times.768) with high refresh rates (e.g., 72 Hz), the pixel rate is approximately 75 MHz (Megahertz), or 13.33 ns (nanoseconds) per pixel. This means that for this high resolution and refresh rate, it is necessary to access video memory once every 53.33 ns. While this is not impossible using current technology, it is certainly very challenging, and leaves virtually no time for the host computer to access the video frame buffer memory. Only vertical and horizontal re-trace intervals (the time while the video monitor beam is invisibly "resetting" itself) is available for host computer access, i.e., a very small percentage of the time.
If the video memory bus width were widened to 64 bits, however, it becomes necessary to access the video frame buffer memory only once every 106.66 ns. At video memory bus width of 128 bits, the required access rate drops to once every 213.33 ns. At these reduced access times, it is possible to interleave host computer memory accesses with display refresh accesses without disrupting the display. Alternatively, it is possible to use slower DRAMs.
In practice, however, such wide bus widths are not practical for a number of reasons. For example, a 128 bit wide video memory bus requires 128 video data pins on the video controller, and enough printed circuit board area to route the 128 associated signal traces from the pins of the video controller to the video memory chips. As a result, the lengths of the signal traces increase, and parasitic capacitances, induced noise and crosstalk between signal traces increase. The increased lengths of the signal traces and increased parasitic capacitances serve to reduce the effective speed of the video memory by increasing the signal propagation delay across the signal traces. Further, very wide memory bus widths require a greater number of relatively smaller memory chips, increasing both circuit board size and component cost dramatically. As a result, very high performance video systems providing high display resolutions, high refresh rates and higher numbers of bits per pixel (e.g., 24), tend to be large and expensive.
Interlaced operation of video monitors (providing an image in two sweeps of the screen by displaying alternating, interleaved rows of pixels) provides one means for reducing the required memory access time, but the resultant perceived display flicker tends to cause eye strain, and is generally regarded as undesirable or unacceptable.
A further limitation on the performance of video systems is related to package-related delays. Every pin of a package has an associated capacitance, requiring a relatively large driver circuit on the integrated circuit to overcome the capacitance and provide acceptable signal speed. These drivers require a disproportionately large portion of die area, and integrated circuits with very large numbers of pins require very large dies just to provide the required driver circuits. Even if a video memory chip could be designed with zero internal access time, there are lower limits on the pin-related delay times. As memories become faster, the pin-related delays present a larger portion of the total memory access time, thereby placing implicit lower limits on memory access time for any given package.
As a result of the performance limitations discussed hereinabove, many modern computer graphics display systems suffer from a video bandwidth "bottleneck" problem, whereby the host computer is capable of computing pixel values faster than the video controller is capable of accepting them and presenting them to the video frame buffer memory. As a result, overall system performance is negatively affected by delays inherent in the design of the video controller and video frame buffer system. These delays are particularly noticeable at high refresh rates and display resolutions, where display refresh-related demands on the video frame buffer memory are greatest. This bottleneck problem is only partially addressed in some systems by providing a FIFO (e.g. 107 with respect to FIG. 1) for buffering pixel data from the host processor. The data is unloaded from the FIFO by a memory access controller when a break occurs in the display refresh sequence. However, when the host processor attempts to manipulate large amounts of data, the FIFO fills up and the processor is forced to wait. Providing a larger FIFO merely delays the time when the FIFO becomes full. The basic problem is that the processor is capable of putting data into the FIFO at a rate faster than the rate the video frame buffer memory is available for unloading the FIFo.